1. Field of the Invention
The present invention relates to a flat panel display and method of fabricating the same and, more particularly, to an active matrix flat panel display and method of fabricating the same.
2. Description of the Related Art
An active matrix flat panel display can be provided with pixels arranged in a matrix form. In an active matrix flat panel display, the pixel generally comprises at least one thin film transistor, a pixel electrode controlled by the thin film transistor, and an opposite electrode corresponding to the pixel electrode. If an organic emission layer is interposed between the pixel electrode and the opposite electrode, the device is typically described as an organic light-emitting device, whereas if a liquid crystal layer is interposed therebetween, the device is typically called a liquid crystal display.
Such an active matrix flat panel display typically comprises pixels defined by a plurality of gate lines and a plurality of data lines. The pixels can be arranged in a matrix form, and the matrix-like arranged pixels may be referred to as a pixel array. A gate driving circuit applying scan signals to the gate lines in sequence and a data driving circuit applying data signals to the data lines may be placed in the periphery of the pixel array.
Here, the wiring resistance of the gate line can cause the scan signal applied from the gate driving circuit to the gate line to be delayed. Further, the delay of the scan signal can deteriorate the picture quality at the pixels positioned far from the gate driving circuit. Hence, as the flat panel device becomes large, this problem can seriously affect the quality of the image on the flat panel display.
To solve the foregoing problems, another gate driving circuit can additionally be provided in the periphery of the pixel array. Thus one gate line can receive the scan signal from two gate driving circuits at both sides. However, this structure can increase the size of the panel.
Alternatively, to solve the foregoing problems, the gate line may be made thicker, thereby reducing its sheet resistance. However, a thick gate line can cause stress imbalance with other layers.